1. Field of the Invention
This invention relates generally to fabrication of multi-level complex integrated circuits and relates more particularly to means and methods of fabricating a plurality of integrated circuit wafers having imperfect cell yields by utilizing the same common masks for fabricating the alternate layers of dielectric insulation and layers of metalization thereon.
2. Description of the Prior Art
In integrated circuit technology wafers having a nonuniform yield of good cells have heretofore been inter-connected into functional circuit types by producing a plurality of masks tailored for that particular wafer yield distribution, each mask being associated with an individual alternate layer of dielectric insulation or metalization formed in laminae on the wafer. A first one of these masks was utilized during fabrication to define and form feedthroughs or vias in a first layer of insulation exposing the pads of selected good cells at the first layer of metalization on the surface of the wafer. A second mask was utilized to form a second layer of metalization into electrical conductors associated with the vias in the first layer of insulation and cross-unders all routed to the location of vias which were subsequently formed in a second layer of insulation by a third mask. At least one (possibly more) alternate layer of metalization was formed on top of the second layer of insulation and fabricated into interconnect lines and cross-overs as defined by a fourth mask whereupon all of the selected good cells were electrically interconnected into a functionally specified complex integrated circuit.
Thus, it can be seen that this technique required that the multiple masks for each wafer had to be tailored to or laid out for a particular wafer since the yield distribution of usable cells varied from wafer to wafer.